NDLI: VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate

Content Provider	IEEE Xplore Digital Library
Author	Chiwande, S.S. Dakhole, P.K.
Copyright Year	2012
Description	Author affiliation: Department of Electronics; Y.C.C.E. Nagpur, Maharashtra, India (Dakhole, P.K.) \|\| Department of Electronics & Telecomm., Y.C.C.E. Nagpur, Maharashtra, India (Chiwande, S.S.)
Abstract	This paper presents various designs of reversible logic gates used for reversible operation & one of the applications as Carry Skip Adder Block. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation result of forward & backward computation of 4*4 reversible TSG & Fredkin gate. This gate is then used to design four bit Carry Skip Adder block. Methodology used for designing reversible gate is Tanner Tool Version-13 & technology file 0.35 micron. It is shown that the adder architecture designed using TSG & Fredkin gate are much better & optimized as compared to existing four bit Carry Skip Adder in terms of low power dissipation.
Starting Page	370
Ending Page	373
File Size	2250305
Page Count	4
File Format	PDF
ISBN	9781457715457
e-ISBN	9781457715464
DOI	10.1109/ICDCSyst.2012.6188788
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reversible Logic Reversible adder Logic gates CMOS integrated circuits Transistors Reversible gate
Content Type	Text
Resource Type	Article

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