NDLI: Accurate power measurement methodology for VLSI circuits using CAD tools

Content Provider	IEEE Xplore Digital Library
Author	Ajay, G. Rajan, R. Chakravarthi, V.S.
Copyright Year	2012
Description	Author affiliation: Department of Electronics & Communications Engineering, B.N.M.I.T, Bangalore-560075, India (Ajay, G.; Rajan, R.; Chakravarthi, V.S.)
Abstract	Electronic design Automation (EDA) tools are used for design verification before fabrication of the integrated circuits. The accuracy of the power measured using these EDA Tools are overlooked since the approximations are good enough to take design decisions. An error in the range of 9.6 – 14.18% is observed between the power indicated in the circuit by the tool and theoretical calculations. These approximations are not very well documented by the EDA tool vendors. Of late, with IP based design flow, power has been the major parameter to assess the quality of the IP core and accuracy of the power measurement of the CAD tools is important. The EDA simulation tools come with built-in functions to measure the power consumption. [1] In this paper we present different ways of measuring the power of the circuit using the EDA simulation tools and their accuracy when compared with the theoretical computations. Work demonstrates the most appropriate method of power measurement in a circuit using Cadence Virtuoso Analog design environment and its result browser.
Starting Page	607
Ending Page	609
File Size	611076
Page Count	3
File Format	PDF
ISBN	9781457715457
e-ISBN	9781457715464
DOI	10.1109/ICDCSyst.2012.6188642
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design automation Power measurement Current measurement Welding Logic gates Erbium
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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