NDLI: Standby and active leakage current control mechanism of half adder cell

Content Provider	IEEE Xplore Digital Library
Author	Kushwah, Preeti Akashe, Shyam
Copyright Year	2014
Description	Author affiliation: Electronics & Communication Dept., Institute of Technology and Management, Gwalior, India (Kushwah, Preeti; Akashe, Shyam)
Abstract	The proposed paper shows the half adder circuit with low power consumption preferred for arithmetic operations. Leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. In the CMOS circuits Power dissipation occurs due to increasing leakage current in deep-sub micrometer regimes which is becoming a significant contributor as threshold voltage, channel length, and gate oxide thickness are reduced. The half adder circuit composed of XOR gate and AND logic gate, which have many transistor. Power consumption (leakage power) in the CMOS technology half adder circuit achieving better performance for maintain the speed, power dissipation, size, reliability of the device. SVL (Self-controllable Voltage Level) technique provides better leakage power reduction with minimum area and it not only reduces power but also retains data during standby period in half adder. Simulation work has been done in 45 nm technology, in this technology power consumption (leakage power) have provided for half adder circuit.
Starting Page	384
Ending Page	389
File Size	139932
Page Count	6
File Format	PDF
e-ISBN	9781479958719
DOI	10.1109/CIPECH.2014.7019091
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-28
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Leakage Current Logic gates Logic Gate SVL Threshold voltage CMOS integrated circuits Leakage currents Transistors Adders Half Adder
Content Type	Text
Resource Type	Article

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