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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kumar, Sachin Gupta, Jyoti Praveen, Pushkar |
| Copyright Year | 2014 |
| Description | Author affiliation: ECE Department, Ram-Eesh Institute of Engineering & Technology, Greater Noida (Praveen, Pushkar) || ECE Department, National Institute of Technology, Delhi (Gupta, Jyoti) || ECE Department, MERI College of Engineering & Technology, Sampla (Kumar, Sachin) |
| Abstract | The key objective of this project is to design a decoder which can be used for hardware purposes. Hardware, here accompanies with software which is more we can discuss as a Software Defined Radio application. The decoder implemented here offers to new radio equipment (SDR), the flexibility of a programmable system. Nowadays, the behavior of a communication system can be modified by simply changing its software. Large tree decoder can be constructed by reusing smaller similar sub-modules. Thus the structure is symmetric. The symmetric and regular structure of tree decoder makes the system easy to design. The structure obeys regularity and modularity concepts of VLSI circuit, thus is easy to fabricate using cell library elements. Design a Tree Decoder proposed architecture for SDR application on FPGA. The Structures made here are hardware synthesizable on FPGA board and are done in a respective manner. The design to be implementing by using Verilog-HDL language. The Simulation and Synthesis by using ISE Xilinx 13.4 tool. |
| Starting Page | 331 |
| Ending Page | 335 |
| File Size | 265099 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479958719 |
| DOI | 10.1109/CIPECH.2014.7019066 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-11-28 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | FPGA Verilog Logic gates Very large scale integration Hardware Decoding Tree Decoder Field programmable gate arrays Computational intelligence Dynamic Decoder Software radio |
| Content Type | Text |
| Resource Type | Article |
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