NDLI: Nanosecond delay level shifter with logic level correction

Content Provider	IEEE Xplore Digital Library
Author	Gundala, S. Ramanaiah, V.K. Kesari, P.
Copyright Year	2014
Description	Author affiliation: Dept. of ECE, SITAMS, Chittoor, India (Gundala, S.) \|\| UCE, Dept. of ECE, JNTUK, Vizianagaram, India (Kesari, P.) \|\| Dept. of ECE, Yogi Vemana Univ., Proddatur, India (Ramanaiah, V.K.)
Abstract	The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips /Cores uses level shifters and the level shifter will become overhead, when its own power consumption & delay is high. In this paper a nanosecond delay level Shifter with logic level correction circuit is introduced that performs level up shifting as well as logic level correction to keep the VOUT stable, equals to VDD or VSS with low power consumption. The circuit is designed and simulated in a 90nm process technology. The proposed technique is a unique component, will comprise a feedback network to keep the output as stable as possible. Robustness of the new level shifter design has examined at an operating frequencies of 10 KHz, 500 KHz, & 1 MHz with varying load of 10 fF to 70 fF and varying temperature from - 20 °C to 70 °C. The proposed design reliably shifts 0.4V input signal to 1V output signal with a delay as low as 0.8ns and average power consumption of 80nW at a frequency of 1MHz.
Starting Page	1
Ending Page	5
File Size	280117
Page Count	5
File Format	PDF
e-ISBN	9781479954964
DOI	10.1109/ICAECC.2014.7002446
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET Power demand Level shifter Power consumption Nanosecond Logic gates Delays Error correction Digital audio players Delay Multiple supply voltage
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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