NDLI: Energy-efficient Level Shifter topology

Content Provider	IEEE Xplore Digital Library
Author	Llanos, R. Sousa, D. Terres, M. Bontorin, G. Reis, R. Johann, M.
Copyright Year	2015
Description	Author affiliation: Inst. de Inf., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil (Llanos, R.; Sousa, D.; Terres, M.; Bontorin, G.; Reis, R.; Johann, M.)
Abstract	Level Shifters (LS) are essential components of integrated circuits with multiple power supply. They work as voltage scaling interfaces between different power domains. In this paper, we present an energy-efficient level shifter with low area topology. It requires only one power rail and can operate nearby the threshold voltage. We validated the proposed topology with simulations on an IBM 130nm CMOS technology. We compared our topology with traditional LS, like the Differential Cascode Voltage Switch (DCVS) or the Puri's topology. The proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri's level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. In addition, our level shifter was the only one capable to work at 35% of the nominal supply.
Starting Page	148
Ending Page	151
File Size	1894571
Page Count	4
File Format	PDF
e-ISBN	9781467394192
DOI	10.1109/PATMOS.2015.7347600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-01
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuits Power demand Level shifter Delay effects Topology Delays Low power Transistors Power-delay product Multiple supply voltage
Content Type	Text
Resource Type	Article

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