NDLI: Design and implementation of WDF for digital down converter on FPGA for LTE application

Content Provider	IEEE Xplore Digital Library
Author	Mani, R.M. Rasheed, A.I.
Copyright Year	2014
Description	Author affiliation: Electron. & Electr. Eng. Dept., M.S. Ramaiah Univ. of Appl. Sci., Bangalore, India (Mani, R.M.; Rasheed, A.I.)
Abstract	As technology is growing wireless communication is also rapidly growing and finding potential application in industries. Development of highly efficient DDC architecture is very important since with rapid technology growth need for complex services are increasing demanding for high data rate transmission and high speed multimedia services. In DDC system two major operations are carried out. First one is frequency translation and second is channel filtering. Different chain of decimation filters can be used to perform channel filtering and decimation operation. Digital IIR filter known as Wave Digital Filter is used as decimator as it offers guaranteed stability, low passband sensitivity and regular structures and also lower order to meet the desired specifications. This paper describes the modeling and analyzing of the Lattice WDF structure using Simulink blocks and Xilinx black box to be implemented in DDC system as first stage to perform decimation operation. The design parameters are sampling frequency, passband frequency, stopband frequency, passband ripple and stopband attenuation defining the gamma and alpha coefficients of the WDF. The proposed filter performs decimation by factor of 2 and also resulting in overall less resource utilization on implementing the modified DDC system on FPGA platform making it attractive for LTE application.
Starting Page	1
Ending Page	4
File Size	453998
Page Count	4
File Format	PDF
e-ISBN	9781479954964
DOI	10.1109/ICAECC.2014.7002447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Baseband DDC Finite impulse response filters FPGA IIR filters WDF Filtering theory Hardware LTE Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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