NDLI: Performance analysis of cluster based 3D routing algorithms for NoC

Content Provider	IEEE Xplore Digital Library
Author	Viswanathan, N. Paramasivam, K. Somasundaram, K.
Copyright Year	2011
Description	Author affiliation: Department of Mathematics, Amrita Vishwa Vidyapeetham, Coimbatore -641 112, India (Somasundaram, K.) \|\| Dept. of Electronics and Communication Engineering, Mahendra Engineering College, Namakkal - 637 503, India (Viswanathan, N.) \|\| Dept. of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Erode -638 401, India (Paramasivam, K.)
Abstract	In the nano scaled transistors integration era, interconnection of IP blocks and data exchange among the IP blocks are crucial concerns in System on Chip (SoC). Network-on-Chip (NoC) is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In deep sub-micron regime, 3D NoC becomes an emerging research area in recent years as the three dimensional (3D) integrated circuits (ICs) can offer shorter interconnection wire and dissipate lesser power. Major area of the 3D NoC research is network topology and routing techniques. In this paper, we present an NS-2 (Network Simulator) simulation environment for two 3D network topologies (GBT and CBT) and cluster based routing algorithms. Simulation results are reported. Simulation results about the relationship between switch buffer size, injected traffic load, packet delay, packet drop probability and energy dissipation are analyzed. On comparing CBT with GBT, a significant performance improvement is demonstrated.
Starting Page	157
Ending Page	162
File Size	730345
Page Count	6
File Format	PDF
ISBN	9781424494781
e-ISBN	9781424494774
DOI	10.1109/RAICS.2011.6069293
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-22
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	NoC SoC Switches Telecommunication traffic Routing Topology Delay Latency Network topology Switch buffer size Wires 3D topology Three dimensional displays Drop probability
Content Type	Text
Resource Type	Article

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