NDLI: Dead-time compensation and realization method for 3-level NPC Inverter

Content Provider	IEEE Xplore Digital Library
Author	Seok-Jin Hong Soo-Cheol Shin Hak-Sung Kim Chung-Yuen Won
Copyright Year	2014
Description	Author affiliation: LG Electron., In-Cheon, South Korea (Soo-Cheol Shin) \|\| Sungkyunkwan Univ., Suwon, South Korea (Seok-Jin Hong; Chung-Yuen Won) \|\| Dongyang Mirea Univ., Gu-ro, South Korea (Hak-Sung Kim)
Abstract	3-Level Neutral Point Clamped (NPC) Inverter has 4 switches in each leg. 2 pairs of switches of the inverter operate complimentarily, S1 and S3 is a pair, the other is S2 and S4. But short circuit fault can be occurred due to a time distinction of turning on/off the switch. Thus, short circuit fault can be prevented by giving dead-time when turning on the switches which complementarily operate mutually. But these dead-time occur error between reference voltage and output voltage of each leg, and distort 3-phase output voltage and current. In this paper, a compensation method and its simple realizing method are proposed to minimize effect from these dead-time. The proposed method is implemented on software and does not require an additional hardware. The proposed method is applied to 3-Level NPC inverter and verified its validity through simulation.
Sponsorship	IEEE Power Electron. Soc.
Starting Page	1
Ending Page	5
File Size	1254374
Page Count	5
File Format	PDF
e-ISBN	9781479942398
DOI	10.1109/ITEC-AP.2014.6941172
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-31
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulated gate bipolar transistors Space vector pulse width modulation Compensation Method Dead-time Deadtime Compensation Compensation Switches Turning Inverters 3-Level NPC Inverter
Content Type	Text
Resource Type	Article

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