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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Parmar, H. Mehta, U. |
| Copyright Year | 2015 |
| Description | Author affiliation: ECC Dept., C.K. Pithwalla Coll. of Eng. & Technol., Surat, India (Parmar, H.) || ECC Dept., Nirma Univ., Ahmedabad, India (Mehta, U.) |
| Abstract | Increase in design complication for current and future era of microelectronics technologies and mechanisms used for data transmission leads to an increased sensitivity to bit-flip errors. As we know, multiple cores are built in a single system on chip (SoC) and to test that SoC, test vectors are transferred from automatic test equipment (ATE) via serial communication link. Now if there is a defect in this communication link, data may flip and creates an error. Such error can lead to an unexpected behavior of the system, loss in data uniformity and results in unreliable system. This paper proposes the new solutions to resolve such bit flip effect. Here Hamming code based technique is used on different compressed vlsi test data to resolve bit flip effect and the results are evaluated and analyzed based on their fault coverage. The obtained simulation results show the productiveness of the proposed solutions. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 213270 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479917433 |
| DOI | 10.1109/ISVDAT.2015.7208099 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-26 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Compression Bit overhead Very large scale integration Area overhead Encoding Decoding Circuit faults Bit flip error ATE Fault coverage Benchmark testing Parity check codes Error correction codes |
| Content Type | Text |
| Resource Type | Article |
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