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2015 19th International Symposium on VLSI Design and Test

Design and development of cantilever-type MEMS based piezoelectric energy harvester

Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology

Thermal aware AND-OR-XOR network synthesis

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks

Improved supply regulation and temperature compensated current reference circuit with low process variations

CORDIC on a configurable serial architecture for biomedical signal processing applications

High-performance multiplierless DCT architecture for HEVC

Case study: Re-visiting SoC verification challenges and best practices

On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints

Area optimized CMOS layouts of a 50 Gb/s low power 4:1 multiplexer

Bipolar voltage level shifter

On-chip CMOS temperature sensor with current calibrated accuracy of −1.1°C to +1.4°C (3σ) from −20°C to 150°C

High speed self biased current sense amplifier for low power CMOS SRAM's

σLBDR: Congestion-aware logic based distributed routing for 2D NoC

Sensitivity analysis of DRV for various configurations of SRAM

Defect characterization and testing of QCA devices and circuits: A survey

A novel dual multiplier floating point multiply accumulate architecture

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies

A framework for thermal aware reliability estimation in 2D NoC

An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow

MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals

A novel approach to reusable time-economized STIL based pattern development

Super-scale architecture enhancement of LEON3 core for DSP application

$C^{2}-DLM:$ Cache coherence aware dual link mesh for on-chip interconnect

A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS

An inductorless receiver front-end for multiband wireless applications

A novel adiabatic SRAM cell implementation using split level charge recovery logic

Realistic dynamic timing verification for complex mixed signal hard macro's using UVM

Implementation of high speed radix-10 parallel multiplier using Verilog

Implementation of high speed radix-10 parallel multiplier using Verilog

Timing model for two stage buffer and its application in ECSM characterization

Performance optimization of real time control systems using variable time period

Intuitive design of PTAT and CTAT circuits for MOSFET based temperature sensor using Inversion Coefficient based approach

Power aware cache miss reduction by energy efficient victim retention

An efficient searching mechanism for dynamic NUCA in chip multiprocessors

Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFET

Modeling and synthesis of molecular memory

An offset-tolerant self-correcting sense amplifier for robust high speed SRAM

Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET

An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICs

An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budget

A cost-optimal algorithm for guard zone computation including detection and exclusion of overlapping

Real time multisensor Laplacian fusion on FPGA

Partitioning-based test time reduction for core-based 3DICs

Design and simulation of magnetic logic device for next generation data processing

A secure architecture for the design for testability structures

Advanced UPF based voltage-aware verification for IOs

Squarer design with reduced area and delay

A novel ROPUF for hardware security

BONY: An algorithm to generate large synthetic combinational benchmark circuits

Area compact 5T portless SRAM cell for high density cache in 65nm CMOS

Methodology for optimizing ESD protection for high speed LVDS based I/Os

Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell

Design of coherence verification unit for heterogeneous CMPs

A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC

A fault tolerant test hardware for L1 cache module in tile CMPs architecture

Parallel two step random walk algorithm to analyze VLSI power grid networks

A novel VLSI design of DCTQ processor for FPGA implementation

Fault masking in Quantum-dot cellular automata using prohibitive logic circuit

Sensitivity and non-linearity study and performance enhancement in bossed diaphragm piezoresistive pressure sensor

High power gain low noise amplifier design for next generation 1–7GHz wideband RF frontend RFIC using 0.18μm CMOS

Design and analysis of a touch mode MEMS capacitive pressure sensor for IUPC

Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT

An efficient on-chip energy processing circuit for micro-scale energy harvesting systems

Measurement of de-assertion threshold of power-on-reset circuits

Transient current estimation using S3C (Standard cell current transient characterization)

Molecular modeling of Nano bio p-i-n FET

Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay

TSV aware standard cell placement for 3D ICs

Net weighing based timing driven standard cell placer

FPGA based disk controller and photon counter of optical polarimeter

Out of order floating point coprocessor for RISC V ISA

RISC-V out-of-order data conversion co-processor

Design and simulative analysis of a batteryless Teflon coated capacitive pressure sensor for glaucoma diagnosis

A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature compensation for RF application

A small bandwidth microelectromechanical ring resonator-based bandpass filter

Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors

GA based diagnostic test pattern generation for transition faults

Side channel attack resistant architecture for elliptic curve cryptography

Detection and analysis of hardware trojan using scan chain method

Low power and hardware cost STUMPS BIST

Modified low power scan based technique

Instruction cache design space exploration for embedded software applications

Design and implementation of DVB-S2 transport stream for onboard processing satellite

Cryptanalysis of hardware based stream ciphers and implementation of GSM stream cipher to propose a novel approach for designing n-bit LFSR stream cipher

PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits

A new row decoding architecture for fast wordline charging in NOR type Flash memories

Fabrication and characterization of pressure sensor, and enhancement of output characteristics by modification of operating pressure range

Analysis and design guidelines for customized logic families in CMOS

A low-power subthreshold LNA for mobile applications

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance

An all digital delay lock loop architecture for high precision timing generator

Verilog-A implementation of energy-efficient SAR ADCs for biomedical application

Novel design for wideband piezoelectric vibrational energy harvester (P-VEH)

Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology

Multi terminal net routing for island style FPGAs using nearly-2-SAT computation

Implementation of a high speed multiplier for high-performance and low power applications

A novel two phase heuristic routing technique in digital microfluidic biochip

A pipelined memory-efficient architecture for face detection and tracking on a multicore environment

Performance study of side block oxide band gap engineered SONOS: A device simulation approach

A constructive heuristic for application mapping onto an express channel based Network-on-Chip

Particle swarm optimization approach for low temperature BIST

Designing efficient combinational compression architecture for testing industrial circuits

Low power, high speed error tolerant multiplier using approximate adders

Low-leakage architecture for embedded ROM

A methodology to reuse random IP stimuli in an SoC functional verification environment

List of full paper

Introduction to MEMS; their applications as sensors for chemical & bio sensing

Multicore processor — Architecture and programming

Network-on-chip: Current issues and challenges

Power- and thermal-aware testing of VLSI circuits and systems

Real-time embedded systems analysis — From theory to practice

SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applications

Technology scaling and its side effects

18th International Symposium on VLSI Design and Test

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