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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Talukdar, P. |
| Copyright Year | 2015 |
| Description | Author affiliation: Int. Inst. of Inf. Technol., Bangalore, China (Talukdar, P.) |
| Abstract | In this paper we address the problem of generating large combinational circuits with good fan in and fanout distribution, high Rent factor and large number of reconvergent gates. Such circuits are in great demand in testing various circuit related algorithms as bench mark circuits or networks. Generation of such circuits is conjectured to be NP Hard problem and available tools are mostly proprietary in nature and may not be available for academic research purposes. In this paper we present a tool for generating large combinational circuits with desirable properties. Our tool generates a netlist that resemble real designs in terms of Rent parameter (interconnect complexity), net degree distribution, path depth and gate counts. We compare the circuits generated by our method with ISCAS-85 benchmark and OpenCores circuits. Using our method, 500K gates combinational circuit is generated in 8 seconds and 1.5 million gates in 36 seconds respectively. We prove that the circuits generated are acyclic in nature. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 316613 |
| Page Count | 2 |
| File Format | |
| e-ISBN | 9781479917433 |
| DOI | 10.1109/ISVDAT.2015.7208094 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-06-26 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Solid modeling Design automation EDA Circuits Integrated circuit interconnections Benchmark testing Logic gates Combinational circuits Synthetic benchmark |
| Content Type | Text |
| Resource Type | Article |
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