NDLI: An improved unipolar CMOS with elevated body and spacer for low-power application

Content Provider	IEEE Xplore Digital Library
Author	Wei-Han Lee Jyi-Tsong Lin Kai-Cheng Juang Ting-Chung Chang Chih-Kai Huang Chien-Chia Lai Bo-Cheng Yan Yong-Huang Lin
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng., Nat. Sun Yat Sen Univ., Kaohsiung, Taiwan (Wei-Han Lee; Jyi-Tsong Lin; Kai-Cheng Juang; Ting-Chung Chang; Chih-Kai Huang; Chien-Chia Lai; Bo-Cheng Yan; Yong-Huang Lin)
Abstract	Summary form only given. In this paper, we present a novel non-classical NMOS transistor with elevated body and spacer to replace the conventional PMOS for CMOS circuits. By calibrating the parameters from the real measurement for the simulations, the novel non-classical NMOS transistor shows a PMOS-like behavior. The proposed unipolar CMOS can reduce the propagation delay time $(T_{P})$ and power dissipation $(P_{D}).$ The simulation results show that the $T_{P}$ and $P_{D}$ of the unipolar CMOS circuit are 46% and 20% lower than the conventional CMOS inverter. It has been confirmed that the proposed unipolar CMOS can work well for all NOR logic gates, NAND logic gates, ring oscillator and static random-access memory (SRAM) under 0.5V power supply. Thus, the unipolar CMOS is expected as a candidate for low-power application in near future CMOS technology.
Starting Page	1
Ending Page	3
File Size	3392997
Page Count	3
File Format	PDF
ISBN	9781467385688
DOI	10.1109/E3S.2015.7336806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET Random access memory Logic gates CMOS technology Inverters CMOS integrated circuits Propagation delay
Content Type	Text
Resource Type	Article

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