NDLI: Design of programmable Op-Amps with minimized DC variations at output

Content Provider	IEEE Xplore Digital Library
Author	Jahangir, M.Z. Paidimarry, C.S.
Copyright Year	2013
Description	Author affiliation: ECE Dept., Osmania Univ., Hyderabad, India (Jahangir, M.Z.; Paidimarry, C.S.)
Abstract	As Analog CMOS ICs are prone to process variations, a minute change in the WIL ratio during fabrication might vary the specifications of the Op-Amp drastically. It is therefore essential to develop a means by which, the specification of IC can be restored even after fabrication. One such approach is to make Analog ICs programmable, so that the specifications can be restored by applying digital input. But this technique is not direct. It is investigated in our work that this technique drifts the output DC voltage (bias voltage), as the bias current varies and therefore creating threat to linear operation of Op-Amp. In this work, a modified programmable Op-Amp with counter programmable level shifter as third stage is proposed. This circuit reduces the variation of the DC voltage with programming current and allows programming of parameters without affecting the biasing. Our simulations indicate that the modified programmable miller two stage op-amp results in linear variation of Slew Rate with digital input. Programming folded cascode Op-Amp, on the other hand shows considerable variation in gain and phase margin. It is experimentally found that the proposed circuit reduces the effect of DC variation by 70% of the previous work.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	120
Ending Page	125
File Size	573555
Page Count	6
File Format	PDF
e-ISBN	9781479927517
DOI	10.1109/PrimeAsia.2013.6731190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Conferences PhaseMargin (PM) Programming Topology Current generators Asia Analog FC Transistors Integrated circuit modeling Slew-Rate (SR) Gain Op-Amps Gain-Bandwidth (GB)
Content Type	Text
Resource Type	Article

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