NDLI: Robust, ultra fast data sensing technique for low power asymmetrical SRAM with self-shut-off feature

Content Provider	IEEE Xplore Digital Library
Author	Reniwal, B.S. Vishvakarma, S.K. Dwivedi, D.
Copyright Year	2013
Description	Author affiliation: Syst. & Technol. Group, IBM Bangalore, Bangalore, India (Dwivedi, D.) \|\| Sch. of Eng., Electr. Eng., Indian Inst. of Technol. Indore, Indore, India (Reniwal, B.S.; Vishvakarma, S.K.)
Abstract	Single ended data sensing for asymmetrical low voltage memories has become a topic of much interest due to its application in very low energy computing and communication. In this paper, we present an ultra-high-speed (UHS) data sensing scheme for single ended near threshold asymmetric static random access memory (SRAM) design in a 45nm standard CMOS process. The proposed bit-line decoupled single ended sense amplifier (BD-SESA) deactivate a $low-V_{th}$ latch by fixing the gate of NMOS device to ground (gnd) which makes the proposed scheme vulnerable to wrong latching for bitline offset due to process variation. We rigorously investigated the impact of process, voltage and temperature (PVT) variation on sensing delay, standby leakage and sensing failure and achieved commendable improvement in power dissipation and sensing delay. A self shut-off mechanism (SSM) significantly reduces voltage swing at read bit-line (RDBL) which further results in reduced power dissipation. Extensive post-layout simulation has verified that our design is insensitive to bit-line capacitance and achieves sensing delay of 297.7pS and 411.7pS at 1V and 0.8V supply respectively and offers 52.56% and 60.36% better mean with 61. 3% and 19.7% less silicon area than designs in comparison.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	77
Ending Page	82
File Size	1572079
Page Count	6
File Format	PDF
e-ISBN	9781479927517
DOI	10.1109/PrimeAsia.2013.6731182
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches Random access memory Ultra high speed Yield Sensors Delays Power dissipation Transistors SRAM Power MOS devices PVT
Content Type	Text
Resource Type	Article

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