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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jun Tan Yong Lian |
| Copyright Year | 2009 |
| Description | Author affiliation: ECE Department, National University of Singapore, Singapore (Jun Tan; Yong Lian) |
| Abstract | In this paper, we present a low voltage, low power, 2.4-GHz frequency synthesizer designed in 0.35-µm CMOS technology. The frequency synthesizer is implemented with an Integer-N phase-locked loop (PLL). The PLL can achieve a frequency tuning step of 1-MHz and is capable of covering the whole 2.4-GHz ISM band. The voltage controlled oscillator (VCO) output frequency is firstly divided by a novel tri-modulus current-mode prescaler. The prescaler output is converted to rail-to-rail swing and drives the true single phase clocked register (TSPC) CMOS counters. The loop filter is designed to be $2^{nd}$ order and implemented off-chip with passive devices. The post-layout simulation results show that the phase noise of the VCO is −107 dBc/Hz at 1 MHz offset, and the PLL reference spur level of the PLL is below −50 dBc. |
| Starting Page | 13 |
| Ending Page | 16 |
| File Size | 1073005 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424446681 |
| DOI | 10.1109/PRIMEASIA.2009.5397460 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-01-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency synthesizers Low voltage Voltage-controlled oscillators CMOS technology Frequency conversion Rail to rail outputs Phase locked loops Tuning Clocks Counting circuits |
| Content Type | Text |
| Resource Type | Article |
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