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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jianping Hu Jinghong Fu |
| Copyright Year | 2009 |
| Description | Author affiliation: Faculty of Information Science and Technology, Ningbo University, Zhejiang 315211, China (Jianping Hu; Jinghong Fu) |
| Abstract | Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTCMOS (Multi-Threshold CMOS) power-gating scheme for adiabatic sequential circuits based on two-phase CPAL (complementary pass-transistor adiabatic logic) circuits, which can operate in a single-phase power clock by introducing a two-phase power-clock generator. A practical sequential system with a mode-10 counter is demonstrated using the MTCMOS power-gating scheme. All circuits are verified using HSPICE, and BSIM4 model is adopted to reflect the characteristics of the leakage currents. Simulations show that the leakage losses are greatly reduced. |
| Starting Page | 456 |
| Ending Page | 459 |
| File Size | 1237333 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424446681 |
| DOI | 10.1109/PRIMEASIA.2009.5397348 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-01-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS logic circuits Circuit simulation Energy dissipation CMOS process Leakage current Sequential circuits Power system modeling Power generation Clocks Counting circuits |
| Content Type | Text |
| Resource Type | Article |
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