NDLI: Best engineering practice for thermal characterization of stacked dice FPGA devices

Content Provider	IEEE Xplore Digital Library
Author	Raghupathy, A. Hoa Do Philofsky, B. Refai-Ahmed, G.
Copyright Year	2015
Description	Author affiliation: Electron. Cooling Solutions Inc., Santa Clara, CA, USA (Raghupathy, A.) \|\| Xilinx Inc., San Jose, CA, USA (Hoa Do; Philofsky, B.; Refai-Ahmed, G.)
Abstract	This paper presents a couple of new methodologies regarding package characterization. An important shortcoming of the JEDEC methodology for single-die packages is that it does not account for the real-world scenario of a package's boundary condition. A new methodology is proposed to overcome this shortcoming by accounting for typical PCB conductivities and heatsink attachments to packages. The second methodology, presented in the paper, shows a better way to develop DELPHI-based boundary condition independent compact thermal models for 2.5D packages with multiple dies mounted on an interposer. This methodology, based on DELPHI-based techniques, accounts for the interaction between the multiple dies in a package. This is done by modifying the resistors generated from the optimization process. A number of verification cases show good fidelity of the compact thermal model to the detailed model.
File Size	1819097
File Format	PDF
e-ISBN	9781467393850
DOI	10.1109/3DIC.2015.7334591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-31
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Conductivity SSI Package characterization Rjc Rjb Substrates Statcked Silicon Interconnect 2.5D packages JEDEC Heating Thermal conductivity Thermal management Multi-die package Junctions Compact thermal model
Content Type	Text
Resource Type	Article

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