NDLI: A chip-level process for power switching module integration and packaging

Content Provider	IEEE Xplore Digital Library
Author	Liang, Z. van Wyk, J.D. Lee, F.C.
Copyright Year	2004
Description	Author affiliation: Center for Power Electron. Syst., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA (Liang, Z.; van Wyk, J.D.; Lee, F.C.)
Abstract	A process module, incorporating embedding of multiple power semiconductor chips in a flat ceramic frame and planar metallization interconnect technologies, has been developed to fabricate active power chip scale packages (CSP), multichip modules (MCMs), and integrated power electronics modules (IPEMs). This integrated chips technology features structure compactness and process integrity, compared to other multilevel packaging methods. Thus, power switching module, including controller and driver, sensor and filter, and power switches can be manufactured with a planar integration technology and packaged in 3-D form. An example IPEM, incorporating power factor correction (PFC) and DC/DC switching stages for a distributed power system (DPS) front-end converter application, has been fabricated and characterized. The electrical performance improvement, which includes reduction in parasitics and increase in efficiency, has been demonstrated. Furthermore, a highly functional integrated PFC switching module with embedded capacitor, current sensor and doubled side cooling has been fabricated in an integrated planar process scheme. The obtained experimental results are presented with prototypes.
Starting Page	1932
Ending Page	1939
File Size	1195453
Page Count	8
File Format	PDF
ISBN	0780384865
ISSN	01972618
DOI	10.1109/IAS.2004.1348733
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metallization Multichip modules Sensor phenomena and characterization Power electronics Ceramics Chip scale packaging Semiconductor device packaging Power semiconductor switches Electronics packaging Driver circuits
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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