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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mahmud, M.I. Celik-Butler, Z. Hao, P. Hou, F. Amey, B. Khan, T. Huang, W. |
| Copyright Year | 2011 |
| Description | Author affiliation: University of Texas at Arlington, Electrical Engg. Dept., P.O. Box 19072, 76019, USA (Mahmud, M.I.; Celik-Butler, Z.) || Texas Instruments Incorporated, Dallas, 75243, USA (Hao, P.; Hou, F.; Amey, B.) || Freescale Semiconductor Inc., Tempe AZ 85284, USA (Khan, T.; Huang, W.) |
| Abstract | Low frequency noise (LFN) characteristics of high voltage double reduced-surface-field LDMOS with SiO2 as gate dielectric is investigated and the effect of DC stressing has been observed. It has been found that the LDMOS does not follow typical noise behavior of ordinary MOSFETs as extended drain attributes a significant role at higher gate overdrive voltages. Here, separation of the overall measured noise components to three distinct regions is proposed: the channel, the resistive region under the gate oxide and that under the field oxide layer. Induced and inherent noise components coming from the extended drain region under the gate and field oxides are separated from the channel noise by performing noise measurements in DNWell standalone resistors. |
| Starting Page | 352 |
| Ending Page | 355 |
| File Size | 1063350 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457701894 |
| e-ISBN | 9781457701924 |
| DOI | 10.1109/ICNF.2011.5994341 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-06-12 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Degradation Resistors Resistance Induced and inherent noise Noise DNWell LDMOS Logic gates 1/ƒ noise RESURF Noise measurement Stress |
| Content Type | Text |
| Resource Type | Article |
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