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Content Provider | IEEE Xplore Digital Library |
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Author | Serna, N. Verdier, F. |
Copyright Year | 2012 |
Description | Author affiliation: LEAT UNS/CNRS UMR 7268, University of Nice, France (Serna, N.; Verdier, F.) |
Abstract | For helping SoC designers to make right choices at the first development steps, we present here a new Hw/Sw high-level SoC model in order to facilitate the exploration. Because they offer a large optimization capacity, we particularly aim on operating system (OS) services, tasks mapping and some architectural parameters like frequency, supply voltage or data width. Simulation results provide consumption and time metrics and allow to verify our application functional validity. We focalize our work on a realistic mono-processor sensor architecture while aiming a future evolution to multi-processor and dynamically reconfigurable architecture. Our model is based on SystemC and allows very fast co-simulation including C++ tasks, OS and high-level models of the hardware architecture. |
Starting Page | 1 |
Ending Page | 8 |
File Size | 1104181 |
Page Count | 8 |
File Format | |
ISBN | 9781467325707 |
e-ISBN | 9781467325721 |
e-ISBN | 9781467325714 |
DOI | 10.1109/ReCoSoC.2012.6322905 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-07-09 |
Publisher Place | United Kingdom |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Measurement Program processors Memory management Sensor Architecture Embedded Systems Designs Hardware OS services exploration MPRSoC System-on-a-chip Co-simulation Co-Design High-level consumption and time estimations |
Content Type | Text |
Resource Type | Article |
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