NDLI: Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Wattebled, P. Diguet, J. Dekeyser, J.
Copyright Year	2012
Description	Author affiliation: Universite de Bretagne Sud and INRIA Lille-Nord Europe, Lorient, France (Wattebled, P.) \|\| Universite des Sciences et Technologies, LILF-CNRS, Lille, France (Dekeyser, J.) \|\| Universite de Bretagne Sud, Lab-STICC - CNRS, Lorient, France (Diguet, J.)
Abstract	Partial and dynamic reconfiguration provides a relevant new dimension to design efficient parallel embedded systems. However, due to the encasing complexity of such systems, ensuring the consistency and parallelism management at runtime is still a key challenge. So architecture models and design methodology are required to allow for efficient component reuse and hardware reconfiguration management. This paper presents a distributed persistence management model and its implementation for reconfigurable multiprocessor systems on dynamically reconfigurable circuits. The proposed approach is inspired from the well-known component based models used in software applications development. Our model is based on membranes wrapping the systems components. The objective is to improve design productivity and ensure consistency by managing context switching and storage using modular distributed hardware controllers. These membranes are distributed and optimized with the aim to design self-adaptive systems by allowing dynamic changes in parallelism degree and contexts migration. Simulation and synthesis results are given to show performances and effectiveness of our methodology.
Starting Page	1
Ending Page	8
File Size	4044919
Page Count	8
File Format	PDF
ISBN	9781467325707
e-ISBN	9781467325721
e-ISBN	9781467325714
DOI	10.1109/ReCoSoC.2012.6322884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-09
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context Switches Computer architecture Software Hardware IP networks Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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