NDLI: An improved design of virtual output impedance loop for droop-controlled parallel three-phase voltage source inverters

Content Provider	IEEE Xplore Digital Library
Author	Xiongfei Wang Blaabjerg, F. Zhe Chen
Copyright Year	2012
Description	Author affiliation: Department of Energy Technology, Aalborg University, Denmark (Xiongfei Wang; Blaabjerg, F.; Zhe Chen)
Abstract	The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method.
Starting Page	2466
Ending Page	2473
File Size	2769953
Page Count	8
File Format	PDF
ISBN	9781467308021
e-ISBN	9781467308038
e-ISBN	9781467308014
DOI	10.1109/ECCE.2012.6342404
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistance Density estimation robust algorithm Reactive power Inverters Impedance Voltage control
Content Type	Text
Resource Type	Article

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