NDLI: Advanced Methods for High-Speed Template Matching Targeting FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Elfert, P. Tiemerding, T. Diederichs, C. Fatikow, S.
Copyright Year	2014
Description	Author affiliation: Div. for Microrobotics & Control Eng., Univ. of Oldenburg, Oldenburg, Germany (Elfert, P.; Tiemerding, T.; Diederichs, C.; Fatikow, S.)
Abstract	Template matching is an important image processing algorithm for object detection and tracking tasks especially because of its very high accuracy. Yet, one major disadvantage of this algorithm is its very high computational effort due to its high complexity which results in low update rates using conventional software-based systems. Additionally, these systems are often afflicted by latency and jitter. Pre-calculating small and robust templates allows for using FPGA-based template matching as an approach to solve these problems. Therefore, the paper outlines three successive software-based approaches to find these small and robust templates. The first approach contains the basic algorithm and is refined by the following two approaches using pre-processing. The resulting templates allow for using the programmable hardware of an FPGA to cache necessary image information and, more importantly, to derive the best matching of template and source image, which results in high update rates. This paper shows novel approaches to high-speed template matching on FPGAs. The validation of these approaches has shown that the resulting tracking quality and feasibility is highly dependent on the relative size of the template in regard to the object to track. The results show tracking uncertainties between one single pixel for low and hundreds of pixels for high resolution videos.
Starting Page	33
Ending Page	37
File Size	384915
Page Count	5
File Format	PDF
ISBN	9781467367523
DOI	10.1109/ISOT.2014.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automation Image edge detection Robustness Hardware Field programmable gate arrays Videos
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in