NDLI: Interface Conversion Design Based on FPGA-Soft-Macro for EnDat2.2 and RS232/RS485

Content Provider	IEEE Xplore Digital Library
Author	Yang Jian Wang Hanbin Yao Xangqian Wan Sanghong
Copyright Year	2010
Abstract	The EnDat2.2 interface protocol developed by HEIDENHAIN company lately with its high-speed, bi-directional and pure digital features can meet the requirement of rapid responses, dramatically cut down the overall system's cost and greatly reduce the space requirements of the system's installation. Therefore, it is widely used in Numerical control system like CNC system and photoelectric encoder. China's first Micro-area X-ray Fluorescence Analyzer used a HEIDENHAIN encoder with this protocol to improve the three micro-platform positioning accuracy. However, considering the complexity of the connection interface to host computer and the high cost of dedicated interface card, the application adopted a new way to fulfill the serial data's transmission tasks rather than dedicated receiver IC. Based on soft-macro, as well as Field Programmable Gate Array FPGA, the idea here is to provide a general EnDat interface module which has the ability of realizing serial encoder data acquisition (RS232/RS485) of EnDat interface. This paper introduces the design idea partly, focuses on methods of the hardware and software design. It was proved by experiments that this design could implement data acquisition.
Starting Page	5289
Ending Page	5292
File Size	298977
Page Count	4
File Format	PDF
ISBN	9781424468805
e-ISBN	9781424468812
DOI	10.1109/iCECE.2010.1284
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	EnDat protocol Protocols Geology Data acquisition FPGA Serial interface Bidirectional control Computer numerical control Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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