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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rezaeii, A.B. Hasseli, L. Moradi, T. |
| Copyright Year | 2013 |
| Description | Author affiliation: Urmia Grad. Inst., Urmia, Iran (Rezaeii, A.B.; Hasseli, L.; Moradi, T.) |
| Abstract | A 125 MS/s self-latch low-power comparator in 0.35 μm CMOS process is presented. This structure is a rail-to-rail folded-cascode amplifier and a positive feedback connection of two back-to-back inverters in which only reset switches are used for controlling. A limited time is not allocated for the evaluation phase and instead the latch sequence starts itself, only after the evaluated voltage reaches to a desired level. Having sufficient time for producing the necessary evaluated voltage, of course in correct direction, guaranties the validity of the comparator operation; it means higher accuracy. Controlling the comparator is easy due to the special structure(using less controlling switches) and the layout is very compact with die size of about $34*14(μm)^{2}.$ The comparator has been examined in all situations such as different corners, power supply noise of 300 m Vp-p and input voltage range of 1.6 Vp-p with 1 mV accuracy. The total power consumption of the comparator and corresponding readout circuitry is only 300 μW. The results show that the kick-back noise and the clock feed-through are reduced as well. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1364886 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467356343 |
| DOI | 10.1109/IranianCEE.2013.6599865 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-14 |
| Publisher Place | Iran |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Latches Accuracy High resolution Noise Self-latching Control systems Inverters Threshold voltage Low power Clocks Comparator |
| Content Type | Text |
| Resource Type | Article |
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