NDLI: High performance multi-channel data compression chip

Content Provider	IEEE Xplore Digital Library
Author	Nusinov, E. Pasco-Anderson, J.
Copyright Year	1994
Description	Author affiliation: Motorola Codex, Mansfield, MA, USA (Nusinov, E.; Pasco-Anderson, J.)
Abstract	This paper describes the architecture and implementation of the Data Compression Chip (DCC) for high-performance lossless data compression for multi-channel highspeed data networking applications. The DCC implements an improved adaptive string matching algorithm using a new parallel architecture-the Variable Length String Matcher (VLSM). The VLSM quickly performs an otherwise time-intensive string-matching procedure. Furthermore, by avoiding the typical data structures that require very large and fast memory to store a compression vocabulary, the DCC's VLSM minimizes system costs. By maintaining separate vocabularies for multiple channels, the DCC eliminates the loss of compression efficiency otherwise experienced in typical frame-multiplexed or reset-at-frame applications. The DCC uses a high-performance algorithm with a custom parallel architecture to minimize vocabulary memory (VRAM) requirements and provide very high throughput and compression efficiency for multiple channels. The device has been realized in 0.8 micron CMOS technology with a die area of 9.27 mm/spl times/10.0 mm and power dissipation about 1 W at 20 MHz. It employs a 160 pin PQFP package.<>
Starting Page	203
Ending Page	206
File Size	443274
Page Count	4
File Format	PDF
ISBN	0780318862
DOI	10.1109/CICC.1994.379736
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data compression Vocabulary Throughput Microprocessors Data structures Costs CMOS technology Decoding Communication system control User-generated content
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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