NDLI: A high throughput variable length decoder with modified memory based architecture

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A high throughput variable length decoder with modified memory based architecture

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A high throughput variable length decoder with modified memory based architecture

Content Provider	IEEE Xplore Digital Library
Author	Bai-Jue Shieh Yew-San Lee Chen-Yi Lee
Copyright Year	1998
Description	Author affiliation: Inst. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Bai-Jue Shieh)
Abstract	Variable-length code (VLC) is the most popular data compression technique. Therefore, a high throughput variable-length decoder (VLD) is required in many applications. In this paper, we propose two simple modified methods which can increase throughput of memory-based two-bit structure variable-length decoder system. The additional hardware of the modified architecture is a control unit and some memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6 um CMOS process and MPEG2 coding table-15 can achieve 720 M bits/s with 100 MHz clock rate.
Starting Page	486
Ending Page	489
File Size	343123
Page Count	4
File Format	PDF
ISBN	0780344553
DOI	10.1109/ISCAS.1998.706982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Decoding Memory architecture Lab-on-a-chip Clocks Hardware Data compression Control systems Arithmetic CMOS process
Content Type	Text
Resource Type	Article

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