NDLI: A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

Content Provider	IEEE Xplore Digital Library
Author	Sang-Soo Lee Boling, E. Kuo, A. Rogenmoser, R.
Copyright Year	2013
Description	Author affiliation: SuVolta Inc., Los Gatos, CA, USA (Sang-Soo Lee; Boling, E.; Kuo, A.; Rogenmoser, R.)
Abstract	A process monitor based on slew-rate measurement has been applied to a body bias control system to detect the process corners and adjust the body bias voltage necessary to meet the power and performance requirements for CMOS circuits. The process monitor consists of N- and P- type slew generators, pulse generator, pulse extender, counter and control circuits. A new analog pulse extender has been developed to increase the pulse width for easy characterization of process corners in practical systems. Circuit description, design considerations, and measured results of the process monitor and body bias generator circuits in 55nm CMOS process are presented. Active circuit area for the process monitor and body bias generator are 0.023 $mm^{2}$ and 0.013 $mm^{2}$ and power dissipation for process monitor and bias generator are 400 μW and 55 μW using a 0.9 V supply. Measured silicon results match with simulation results and show correct operation of the circuits.
Starting Page	1
Ending Page	4
File Size	1177545
Page Count	4
File Format	PDF
ISBN	9781467361460
DOI	10.1109/CICC.2013.6658516
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Monitoring Generators Transistors Process control Pulse measurements Bidirectional control System-on-chip
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Research on ERT system denoising technology excited by bi-directional pulse current

A LDO regulator with slew-rate enhancement circuit for low-power SoC

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

High Slew Rate op-amp design for low power applications

Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring

Off-state leakage power reduction by automatic monitoring and control system.

A dead-time generator based on OPA slew rate for consumer electronic applications

Adaptive biased operational amplifier with improved Slew-Rate

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

Similar Documents

Research on ERT system denoising technology excited by bi-directional pulse current

A LDO regulator with slew-rate enhancement circuit for low-power SoC

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection

High Slew Rate op-amp design for low power applications

Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring

Off-state leakage power reduction by automatic monitoring and control system.

A dead-time generator based on OPA slew rate for consumer electronic applications

Adaptive biased operational amplifier with improved Slew-Rate

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications