NDLI: A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

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2015 IEEE Custom Integrated Circuits Conference (CICC)

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

Table of contents

Steering committee

Educational sessions

Welcome from the CICC committee

40V MESFETs fabricated on 32nm SOI CMOS

Recent advances in GaN power electronics

Prospective for nanowire transistors

Interconnect and package design of a heterogeneous stacked-silicon FPGA

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter

Current-steering pre-emphasis transmitter with continuously tuned line terminations for optimum impedance match and maximum signal drive range

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

Design considerations for low-power receiver front-end in high-speed data links

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS

Compact high-power 60 GHz power amplifier in 65 nm CMOS

CMOS low-power transceivers for 60GHz multi Gbit/s communications

A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line

Transformer-based dual-band VCO and ILFD for wide-band mm-Wave LO generation

Paper not available

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor

Paper not available

Paper not available

A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs

An 8-Bit 4-GS/s 120-mW CMOS ADC

A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers

A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS

A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation

Thermal noise modeling of nano-scale MOSFETs for mixed-signal and RF applications

A model-agnostic technique for simulating per-element distortion contributions

Corner models: Inaccurate at best, and it only gets worst …

Energy centric model of SRAM write operation for improved energy and error rates

SRAM read current variability and its dependence on transistor statistics

Mismatch characterization of small metal fringe capacitors

A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation

Energy-efficient recognition and mining processor using scalable effort design

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications

SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process

Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS

Distributed clock generator for synchronous SoC using ADPLL network

A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms

Parallel gain enhancement technique for switched-capacitor circuits

Sampling circuits that break the kT/C thermal noise limit

Blind background calibration of harmonic distortion based on selective sampling

CMOS millimeter wave phase shifter based on tunable transmission lines

Charge steering: A low-power design paradigm

A broadband biosensor interface IC for miniaturized dielectric spectroscopy from MHz to GHz

Capacitive proximity communication with distributed alignment sensing for origami biomedical implants

An active rectifier/regulator combo circuit for powering biomedical implants

65nW CMOS temperature sensor for ultra-low power microsystems

Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor array

ST-MRAM fundamentals, challenges, and applications

Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure

A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with $1.39mm^{2}$ per MB

A bit-by-bit re-writable Eflash in a generic logic process for moderate-density embedded non-volatile memory applications

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory

A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA

A 50MHz bandwidth, 10-b ENOB, 8.2mW VCO-based ADC enabled by filtered-dithering based linearization

A reconfigurable ΔΣ modulator with up to 100 MHz bandwidth using flash reference shuffling

A 10-MHz bandwidth 70-dB SNDR 640MS/s continuous-time ΣΔ ADC using Gm-C filter with nonlinear feedback DAC calibration

Algorithmic nonlinear macromodeling: Challenges, solutions and applications in Analog/Mixed-Signal validation

Event-driven simulation of Volterra series models in SystemVerilog

A Verilog piecewise-linear analog behavior model for mixed-signal validation

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013)

Structure-aware high-dimensional performance modeling for analog and mixed-signal circuits

A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC

A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps

A novel OTA-based fast lock PLL

Design metrics for blind ADC-based wireline receivers

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

A 9.2-GHz digital phase-locked loop with peaking-free transfer function

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

Nonlinearity cancellation in digital PLLs (Invited paper)

Hybrid transformer-based tunable integrated duplexer with antenna impedance tracking loop

A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design

A lumped component programmable delay element for Ultra-Wideband beamforming

The past present and future of design-technology co-optimization

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Foundations for scaling beyond 14nm

BIF — Battery interface standard for mobile devices

A 40V 10W 93%-efficiency current-accuracy-enhanced dimmable LED driver with adaptive timing difference compensation for solid-state lighting applications

A stackable switched-capacitor DC/DC converter IC for LED drivers with 90% efficiency

A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters

A compact 120-MHz 1.8V/1.2V dual-output DC-DC converter with digital control

A monolithic digitally controlled ripple-based DC-DC converter with digital inductor current sensor

A fully integrated battery-connected switched-capacitor 4:1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling

A 110nA synchronous boost regulator with autonomous bias gating for energy harvesting

A power sensor with 80ns response time for power management in microprocessors

Discretization and discrimination methods for design, verification, and testing of analog/mixed-signal circuits

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering

Circuit reliability simulation using TMI2

Scalable behavior modeling for 3D field-programmable ESD protection structures

Quasi-3D method: Time-efficient TCAD and mixed-mode simulations on finFET technologies

Gate stack resistance and limits to CMOS logic performance

IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm

Advances in the design of wideband receivers

An asymmetric dual-channel reconfigurable receiver for GNSS in 180nm CMOS

A 5-GHz 11.6-mW CMOS receiver for IEEE 802.11a applications

An adaptive predistorter for wireless LAN RFSoC with embedded PA and T/R switch in 55nm CMOS

A 116nW multi-band wake-up receiver with 31-bit correlator and interference rejection

A 11μW Sub-pJ/bit reconfigurable transceiver for mm-sized wireless implants

Concurrent design of ESD protection and ICs for optimization and prediction

Characterization of matching variability and low-frequency noise for mixed-signal technologies

Single-inductor-multiple-output DC-DC converter design

Advanced digital phase-locked loops

Design for nanoscale patterning

Low power chip & system design for biomedicai applications

Trends, Possibilities and Limitations of Silicon Photonic Integrated Circuits and Devices

A/D converter circuit and architecture design for high-speed data communication

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator

High-sensitivity photodetection sensor front-end, detecting organophosphourous compounds for food safety

A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding

Analysis of deviation from Pelgrom scaling law in Vth variability of pocket-implanted MOSFET

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

Highly efficient CMOS rectifier assisted by symmetric and voltage-boost PV-cell structures for synergistic ambient energy harvesting

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications

Comparison of modeling approaches through hierarchical behavioral modeling of a GNSS receiver front-end

Pulse amplification based dynamic synchronizers with metastability measurement using capacitance de-rating

FireBird: PowerPC e200 based SoC for high temperature operation

A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme

A 15-bit binary-weighted current-steering DAC with ordered element matching

45pW ESD clamp circuit for ultra-low power applications

A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation

A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS

A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI

A fully integrated highly linear receiver with automatic IP2 calibration schemes for multi-standard applications

A 500 MS/s 76dB SNDR continuous time delta sigma modulator with 10MHz signal bandwidth in 0.18μm CMOS

A 0.1–3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

A direct-battery hookup, fully integrated stereo headphone module with 82 mW output power and 110 dB PSRR

A fast-locking digital DLL with a high resolution time-to-digital converter

A stochastic sampling time-to-digital converter with tunable 180–770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset

A 50 μW/Ch artifacts-insensitive neural recorder using frequency-shaping technique

A bipolar >40-V driver in 45-nm SOI CMOS technology

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme

Design for manufacturing layout analyses correlate layout to physico-chemical yield loss mechanisms

A split-foundry asynchronous FPGA

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

AOT-controlled dual-mode AVP buck regulator with AEAF mechanism

Switched-capacitor filter based Type-III compensation for switched-mode Buck converters

Estimation of passive mixer output bandwidth using switched-capacitor techniques

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core

A general-purpose vision processor with 160×80 pixel-parallel SIMD processor array

A programmable analog frequency-locked loop for VCO characterization and test with 8 ppm resolution

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics

A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS

A fully differential ultra-compact broadband transformer based quadrature generation scheme

A −173 dBc/Hz @ 1 MHz offset Colpitts oscillator using AlN contour-mode MEMS resonator

An ultra-broadband compact mm-wave butler matrix in CMOS for array-based MIMO systems

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC

A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy

A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS

A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal

A 4–15-GHz ring oscillator based injection-locked frequency multiplier with built-in harmonic generation

Power management circuits for a 15-μA, implantable pressure sensor

A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays

Wireline transmitter and receiver design techniques

Electrical and photonic I/O test and debug

Nyquist rate A/D converters

Variation and analog modeling

Energy efficient SoC design

Analog techniques I

Microsystems for biomedical and sensing applications

Advanced memory topics

Oversampled ADC's

AMS system simulation techniques

Analog techniques II

High-speed wireline timing recovery & PLLs

RF building blocks

Power management

AMS verification in advanced technologies

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

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A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

Content Provider	IEEE Xplore Digital Library
Author	Yung-Hui Chung Meng-Hsuan Wu Hung-Sung Li
Copyright Year	2013
Description	Author affiliation: MediaTek Inc., Hsinchu, Taiwan (Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li)
Abstract	A 12-bit SAR ADC is presented with a FoM of 11.7fJ/conversion-step. The ADC employs a two-step decision DAC switching technique for improving the ADC's linearity and switching energy using smaller input capacitance. It effectively eliminates the largest capacitor-DAC middle-code transition error. The proposed switching scheme can also tolerate DAC settling errors without requiring redundant capacitors. The ADC core occupies an area of $0.079mm^{2}$ in a 0.11μm CMOS process. At 1MS/s, it consumes 24μW from a 0.9V supply. Measured DNL and INL are 0.29LSB and 0.55LSB respectively. Measured SNDR and SFDR are 68.3dB and 82dB respectively. Measured ENOB is 11.05b at the Nyquist-rate input.
Starting Page	1
Ending Page	4
File Size	911932
Page Count	4
File Format	PDF
ISBN	9781467361460
DOI	10.1109/CICC.2013.6658424
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Capacitors Capacitance Linearity CMOS process CMOS integrated circuits Power demand
Content Type	Text
Resource Type	Article

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