NDLI: A substrate noise analysis methodology for large-scale mixed-signal ICs

Content Provider	IEEE Xplore Digital Library
Author	Wen Kung Chu Verghese, N. Heayn-Jun Cho Shimazaki, K. Tsujikawa, H. Hirano, S. Doushoh, S. Nagata, M. Iwata, A. Ohmoto, T.
Copyright Year	2003
Description	Author affiliation: Cadence Design Syst. Inc., San Jose, CA, USA (Wen Kung Chu; Verghese, N.; Heayn-Jun Cho)
Abstract	A substrate noise analysis methodology is described that simulates substrate noise waveforms at sensitive locations of large-scale mixed-signal ICs. Simulation results for a 7.3 mm/spl times/7.3 mm chip with 500 k devices, obtained in a few hours on an engineering server, show good correlation with silicon measurements as testing conditions are varied. An analysis of the substrate and package reveals the importance of modeling inductive coupling between neighboring switching and quiet ground pins due to the substrate return of currents between them.
Sponsorship	IEEE Solid-State Circuits Soc. IEEE Electron Devices Soc
Starting Page	369
Ending Page	372
File Size	344157
Page Count	4
File Format	PDF
ISBN	0780378423
DOI	10.1109/CICC.2003.1249420
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Circuit simulation Circuit noise Semiconductor device measurement Packaging Noise measurement Switching circuits Voltage Information analysis Integrated circuit noise
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A substrate noise circuit for accurately testing mixed-signal ICs

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies

A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

Fast parasitic extraction for substrate coupling in mixed-signal ICs

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

Simulation and measurement of supply and substrate noise in mixed-signal ICs

SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs

Test circuits for substrate noise evaluation in CMOS digital ICs

A substrate noise analysis methodology for large-scale mixed-signal ICs

Similar Documents

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

A substrate noise circuit for accurately testing mixed-signal ICs

Analysis and Measurement of Crosstalk Effects on Mixed-Signal CMOS ICs With Different Mounting Technologies

A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

Fast parasitic extraction for substrate coupling in mixed-signal ICs

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

Simulation and measurement of supply and substrate noise in mixed-signal ICs

SUBWAVE: a methodology for modeling digital substrate noise injection in mixed-signal ICs

Test circuits for substrate noise evaluation in CMOS digital ICs

A substrate noise analysis methodology for large-scale mixed-signal ICs