NDLI: Novel VLIW code compaction method for a 3D geometry processor

Content Provider	IEEE Xplore Digital Library
Author	Suzuki, H. Making, H. Matsuda, Y.
Copyright Year	2000
Description	Author affiliation: Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan (Suzuki, H.)
Abstract	A VLIW (very long instruction word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a single SIMD (single instruction, multiple data) architecture. To solve the code bloat problem in common with VLIW architectures, the proposed method enables one to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the compaction method are compared to a reference processor with the same instruction set and the same building blocks. The speed of the FP-VLIW is the fastest in all test cases. It is 26%-30% faster than the reference processor. The proposed compaction method keeps the 94% code density of the reference processor. The FP-VLIW architecture with the code compaction achieves 1.2-1.3 times of the speed performance without significant code-density deterioration.
Starting Page	555
Ending Page	558
File Size	432472
Page Count	4
File Format	PDF
ISBN	0780358090
DOI	10.1109/CICC.2000.852729
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-24
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Compaction Geometry Computer architecture Hardware Costs Software tools Containers Large scale integration Programming profession
Content Type	Text
Resource Type	Article

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