NDLI: Analysis of jitter due to power-supply noise in phase-locked loops

Content Provider	IEEE Xplore Digital Library
Author	Heydari, P. Pedram, M.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA (Heydari, P.)
Abstract	Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. Finally the timing jitter of the PLL is predicted in response to the VCO phase noise. A PLL circuit has been designed in 0.35 /spl mu/m CMOS process, and our mathematical model was applied to determine the timing jitter. Experimental results prove the accuracy of the predicted model.
Starting Page	443
Ending Page	446
File Size	454552
Page Count	4
File Format	PDF
ISBN	0780358090
DOI	10.1109/CICC.2000.852704
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-24
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Phase locked loops Circuit noise Timing jitter Voltage-controlled oscillators Very large scale integration Power supplies Radio frequency RF signals Rails
Content Type	Text
Resource Type	Article

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