NDLI: CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator

Content Provider	IEEE Xplore Digital Library
Author	Foley, D.J. Flynn, M.P.
Copyright Year	2000
Description	Author affiliation: Nat. Microelectron. Res. Centre, Univ. Coll. Cork, Ireland (Foley, D.J.)
Abstract	This paper describes a low voltage, low jitter clock synthesizer and a temperature compensated tunable oscillator. Both of these circuits employ a self-correcting Delay Locked Loop (DLL). The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer and provides temperature compensated biasing for the tunable oscillator. With a 2 V supply the measured RMS jitter for the 1 GHz synthesizer output was 3.2 ps. With a 3.3 V supply RMS jitter of 3.1 ps was measured for a 1.6 GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0 to 85/spl deg/C. The circuits were fabricated on a generic 0.5 /spl mu/m digital CMOS process.
Starting Page	371
Ending Page	374
File Size	545784
Page Count	4
File Format	PDF
ISBN	0780358090
DOI	10.1109/CICC.2000.852688
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-24
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Clocks Synthesizers Temperature Delay Tunable circuits and devices Oscillators Frequency Phase locked loops Phase detection
Content Type	Text
Resource Type	Article

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CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator