NDLI: A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

Content Provider	IEEE Xplore Digital Library
Author	Melly, T. Porret, A.-S. Enz, C.C. Kayal, M.
Copyright Year	1998
Description	Author affiliation: Electron. Lab., Fed. Inst. of Technol., Lausanne, Switzerland (Melly, T.)
Abstract	A low-power and low-voltage (LP/LV) RF front-end operating at 430 MHz and implemented in a standard 0.5 /spl mu/m digital CMOS process is described. Specific LP/LV bias techniques and design tradeoffs are discussed and their application to the design of a fully integrated direct-conversion receiver is presented. The RF building blocks including a 200 /spl mu/A LNA, two different 50 /spl mu/A mixers and a ring-oscillator with differential I-Q outputs consuming 300 /spl mu/A at 430 MHz, have been manufactured and their performances measured. Taking into account the severe power budget, a total double sideband (DSB) noise figure of 17 dB was achieved, together with a spurious free dynamic range of 55 dB at 60 kHz bandwidth, which is sufficient for the targeted application.
Starting Page	503
Ending Page	506
File Size	441082
Page Count	4
File Format	PDF
ISBN	0780342925
DOI	10.1109/CICC.1998.695028
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Radio frequency Frequency shift keying Energy consumption Voltage 1f noise CMOS technology Noise figure Dynamic range Bandwidth
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1.2 V, 430 MHz, 4 dBm power amplifier and a 25 /spl mu/W front-end, using a standard digital CMOS process

A 2.4-GHz sub-mW CMOS current-reused receiver front-end for wireless sensor network

A 4.5-mW 900-MHz CMOS receiver for wireless paging

Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver

An integrated 17 GHz front-end for ISM/WLAN applications in 0.13 /spl mu/m CMOS

A 0.5 V 900 MHz CMOS Receiver Front End

A 1.2v inductorless receiver front-end for multi-standard wireless applications.

A direct conversion CMOS RF front-end for IEEE 802.11a wireless LAN

A 2.4-GHz CMOS RF front-end for wireless sensor network applications

A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]

Similar Documents

A 1.2 V, 430 MHz, 4 dBm power amplifier and a 25 /spl mu/W front-end, using a standard digital CMOS process

A 2.4-GHz sub-mW CMOS current-reused receiver front-end for wireless sensor network

A 4.5-mW 900-MHz CMOS receiver for wireless paging

Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver

An integrated 17 GHz front-end for ISM/WLAN applications in 0.13 /spl mu/m CMOS

A 0.5 V 900 MHz CMOS Receiver Front End

A 1.2v inductorless receiver front-end for multi-standard wireless applications.

A direct conversion CMOS RF front-end for IEEE 802.11a wireless LAN

A 2.4-GHz CMOS RF front-end for wireless sensor network applications

A 1.3 V low-power 430 MHz front-end using a standard digital CMOS process [ISM wireless link]