NDLI: Towards one chip HDTV MPEG2 encoder LSI

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Towards one chip HDTV MPEG2 encoder LSI

Content Provider	IEEE Xplore Digital Library
Author	Li Jiang Dongju Li Haba, S. Chawalit Kunieda, H.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan (Li Jiang)
Abstract	In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with window MSPA architecture, the hardware cost is reduced without much PSNR performance degradation. The core of the test chip working at 83 MHz performs a search range of /spl plusmn/67 for image size of 1920/spl times/1152 and achieves video rate of 60 field/s. It can be used for HDTV purposes. The chip size is 4.8 mm/spl times/4.8 mm with 0.5 /spl mu/m 2-level metal CMOS technology.
Starting Page	173
Ending Page	176
File Size	529701
Page Count	4
File Format	PDF
ISBN	0780342925
DOI	10.1109/CICC.1998.694930
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	HDTV Large scale integration Hardware CMOS technology Motion estimation Costs PSNR Degradation Testing Performance evaluation
Content Type	Text
Resource Type	Article

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