NDLI: A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications

Content Provider	IEEE Xplore Digital Library
Author	Hanami, A. Scotzniovsky, S. Ishihara, K. Matsumura, T. Takeuchi, S. Ohkuma, H. Nishigaki, K. Suzuki, H. Kazayama, M. Yoshida, T. Tsuchihashi, K.
Copyright Year	1998
Description	Author affiliation: Syst. LSI Div., Mitsubishi Electr. Corp., Hyogo, Japan (Hanami, A.)
Abstract	A wide range motion estimation with exhaustive search is the best approach for high quality encoding applications. To perform the required computational power, a 165 GOPS (giga operations per second) exhaustive motion estimation processor ME3 has been developed. The ME3 is powerful enough to realize a range of -64/+63 pixels horizontally and -32/+31 pixels vertically with a single chip. A dual-array architecture supports not only high calculation power but also luminance and chrominance based search to increase picture quality. Also, the ME3 outputs extra vectors as candidates to enhance the picture quality. Using a multi-chip configuration, the exhaustive search range can be easily expanded to meet the requirements of MP@HL encoder. It is implemented using 0.35 /spl mu/m CMOS technology and contains 1.9 million transistors in an area of 8.5/spl times/8.5 mm/sup 2/.
Starting Page	169
Ending Page	172
File Size	535118
Page Count	4
File Format	PDF
ISBN	0780342925
DOI	10.1109/CICC.1998.694929
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion estimation Large scale integration Costs Search methods Encoding CMOS technology Adaptive arrays Laboratories Information technology Research and development
Content Type	Text
Resource Type	Article

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