NDLI: An embedded stack microprocessor for SDH telecommunication applications

Content Provider	IEEE Xplore Digital Library
Author	Stadler, M. Thalmann, M. Rower, T. Felber, N. Fichtner, W.
Copyright Year	1998
Description	Author affiliation: Integrated Syst. Lab., Fed. Inst. of Technol., Zurich, Switzerland (Stadler, M.)
Abstract	In this paper we present an application-specific microprocessor core with a stack architecture optimized for use in broadband telecommunication ASICs. The microprocessor was integrated in an application on the same die as the complete data path of an SDH add-drop multiplexer (ADM). It handles over 1 million interrupts per second from 29 asynchronous sources. Due to this high interrupt rate extremely efficient context switching is required: only two extra cycles per interrupt call. The top four stack elements are directly accessable as registers and ALU instructions are computed in parallel with push or pop commands. An independent ALU for address processing enables compact and very efficient code generation. A prototype ASIC has been implemented in 0.8 /spl mu/m CMOS technology.
Starting Page	17
Ending Page	20
File Size	535739
Page Count	4
File Format	PDF
ISBN	0780342925
DOI	10.1109/CICC.1998.694899
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-05-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Synchronous digital hierarchy CMOS technology Add-drop multiplexers Telecommunication switching Registers Computer aided instruction Concurrent computing Prototypes Application specific integrated circuits
Content Type	Text
Resource Type	Article

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