NDLI: Technology decomposition for low-power synthesis

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LIST OF CONTRIBUTORS

A flexible gate array for high speed and high density applications

A 50,000-gate MCM-based PLD for gate array prototyping

Design considerations for high-performance low-power silicon-on-insulator gate arrays

CMOS gate array architecture for digital signal processing applications

A two million gate 0.35 /spl mu/m CMOS ASIC family

The convergence of structured custom and ASIC designs

Design methodology of a test chip for a portable 8ns 10 ports register file

A 32-bit complex-arithmetic integer logic unit with dynamic accuracy

A transformational approach to VHDL and CDFG based high-level synthesis: a case study

BALLISTIC: an analog layout language

Semi-custom ASIC technology trends

A scaled 0.6 /spl mu/m high speed PLD technology using single-poly EEPROM's

Implementing heterogeneous microsystems in a three-dimensional packaging technology

High-level hot carrier reliability-driven synthesis using macro-models

Hot-carrier induced degradation of critical paths modeled by rule-based analysis

Accuracy bounds in switching activity estimation

Circuit techniques for the radiation environment of space

Future directions in silicon ICs for RF personal communications

A 1 GHz quadrature sinusoidal oscillator

An improved 3 V 2 GHz BiCMOS image reject mixer IC

One-chip receiver IC for 2.4 Gb/s optical communication systems

A BiCMOS automatic gain control amplifier for SONET OC-3

Current integrating receivers for high speed system interconnects

Evaluating mixed-signal simulators

Fast parasitic extraction for substrate coupling in mixed-signal ICs

Modeling and analysis of substrate coupling in integrated circuits

A methodology for rapid estimation of substrate-coupled switching noise

New approaches for on-chip power switching noise reduction

Special memory and embedded memory macros in MPEG environment

A 250-MHz skewed-clock pipelined dual-port embedded DRAM

A scalable pipelined architecture for fast buffer SRAM's

A 500-MHz, 0.4-/spl mu/m CMOS, 32-word by 32-bit 3-port register file

2 V 120 nsec 8/16-bit microcontroller with embedded flash EEPROM

A dynamic voltage sensing FIFO suitable for multi-format video systems

Circuit technique for skew-free clock distribution

A low cost, digital microphone chip

FDF, a 512-TAP FIR filter using a mixed temporal-frequential approach

A new high performance digital deflection controller

A stereo vision processor

Low power filtering using approximate processing for DSP applications

Efficient DSP design for vocoder application

A second-order double-sampled delta-sigma modulator

A 14-bit 500 kHz delta-sigma ADC with 16 times oversampling

A single shot sigma delta analog to digital converter for multiplexed applications

An 8-bit 200 Ms/s 500 mW BiCMOS ADC

A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme

A 10 bit low-power CMOS D/A converter with on-chip gain error compensation

A power optimized 13-bit 5M samples/s pipelined analog to digital converter in 1.2 /spl mu/m CMOS

Virtual instruments for development of high performance circuit technologies

A short channel charge LDD-MOSFET model for analog and digital circuits with low overdrive voltage

Accurate MOS device hot carrier models for VLSI reliability simulation

Efficient worst case analysis of integrated circuits

Efficient multi-tone distortion analysis of analog integrated circuits

Rapid estimation of the nonlinear frequency response of switched-capacitor circuits

On-chip cross talk-the new signal integrity challenge

Accurate parasitic resistance extraction for interconnection analysis

Optimal and efficient buffer insertion and wire sizing

Low power IC clock tree design

PCHECK: a delay analysis tool for high performance LSI design

Timing verification of dynamic circuits

An efficient contact placement for custom cell layout synthesis

A fully integrated digital demodulation and forward error correction IC for digital satellite television

A single-chip concatenated FEC decoder

A high-speed, high-resolution analog front end for digital subscriber line applications

A chip set for a digital audio broadcasting channel decoder

A high-performance analog front-end 13-bits linear codec for 3V digital cellular phones

A programmable CDMA IF transceiver ASIC for wireless communications

A low-power baseband receiver IC for frequency-hopped spread spectrum applications

A small-size adder-free /spl pi//4-shift QPSK signal generator

A 2-V, 2-GHz low-power direct digital frequency synthesizer chip set for wireless communication

Analysis, modeling, and simulation of phase noise in monolithic voltage-controlled oscillators

Inductorless oscillator design for personal communications devices-a 1.2 /spl mu/m CMOS process case study

CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

Surface micromachined accelerometers

An accelerometer interface circuit

VRS interface circuit with differential input and variable hysteresis

A high speed distortion correcting mixed signal preprocessor for image scanning

A foveated image sensor in standard CMOS technology

A power modelling and characterization method for logic simulation

Equation based timing: methodology and model for cell libraries

Dual threshold delay model for nonlinear device characterization

Realistic worst-case SPICE file extraction using BSIM3

3-D extraction techniques for signal integrity analysis

A performance-driven router for RF and microwave analog circuit design

A neural network model for propagation delays in systems with high speed VLSI interconnect networks

A chip set architecture for programmable real-time MPEG2 video encoder

A single chip, 5 GOPS, macroblock-level pixel processor for MPEG2 real-time encoding

A chip set for MPEG-2 video encoding

A motion estimation processor for MPEG2 video real time encoding at wide search range

A compact motion estimator with a simplified vector search strategy maintaining encoded picture quality

MPEG audio decoder for consumer applications

10 Gb/s framer/demultiplexer IC for SONET STS-192 applications

A low power 128/spl times/1-bit GaAs FIFO for ATM packet switcher

A 50,000 transistor packet-switching chip for the Starburst ATM switch

An ATM chip set for high performance computer interfaces, affording over 100 Mbps sustained throughput

A time/space switch LSI with a 300-Mb/s CMOS low-power I/O interface

622 Mbit/s board-to-board link in 0.5 /spl mu/m CMOS technology

An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling

An area minimizing layout generator for random logic blocks

A new hierarchical algorithm for transistor placement in CMOS macro cell design

Concurrent logic and layout design system for high performance LSIs

Hierarchical timing-driven floorplanning and place and route using a timing budgeter

An efficient approach for via minimization in multi-layer VLSI/PCB routing

Dynamic bound generation for constraint-driven routing

A module generator for high speed CMOS current output digital/analog converters

Future directions of dynamically reprogrammable systems

A time-multiplexed FPGA architecture for logic emulation

An SRAM-programmable field-configurable memory

FPGA implementation of fuzzy color correction system

A 90.7 MHz-2.5 million transistors CMOS CPLD with JTAG boundary scan and in-system programmability

Logic block and routing considerations for a new SRAM-based FPGA architecture

Structure and concepts for current-based analog scan

Test generation for linear analog circuits

On the practical implementation of mixed analog-digital BIST

Architectural exploration for analog system synthesis

Top-down, constraint-driven design methodology based generation of a second order /spl Sigma/-/spl Delta/ A/D converter

Simulation model transformations for analog hardware description languages

High-speed low-power integrating CMOS sample-and-hold amplifier architecture

High speed switched-current-mode BiCMOS track-and-hold circuit

A low-distortion BiCMOS 7th-order Bessel filter operating at 2.5 V supply

A Videobandwidth Analog Median Circuit

12 V /spl Sigma/-/spl Delta/ class-D amplifier in 5 V CMOS technology

A 35 Mb/s mixed-signal decision-feedback equalizer for disk-drive applications

A 200 MHz 3.3 V BiCMOS class-IV partial-response analog Viterbi decoder

A 0.75-V, 0.7 MHz CMOS 32-bit RISC microprocessor for portable applications

MiniRISC CW4001-a small, low-power MIPS CPU core

An 800 MHz 1-micron CMOS pipelined 8-bit adder using true single-phase logic-flip-flops

A 64 bit carry look-ahead CMOS adder using Modified Carry Select

Leading-zero anticipatory logic for high-speed floating point addition

100 MHz, 0.55 mm/sup 2/, 2 mW, 16-b stacked-CMOS multiplier-accumulator

l00MHz 0.55mm/sup 2/, 2 mW 16-b Stacked-CMOS Multiplier-Accumulator

Standardizing ASIC libraries in VHDL using VITAL: a tutorial

ARSDES: an automated Reed-Solomon decoder and encoder synthesis system

An integrated data path synthesis algorithm based on network flow method

A verification technique for communication hardware and its application to a real chip design

Speeding up power estimation by topological analysis

Technology decomposition for low-power synthesis

I/sub DDQ/ testing and defect classes-a tutorial

Mixed-mode timing simulation for accurate CMOS bridging fault detection

Enhancing the boundary scan standard to test resistively-terminated printed circuit board interconnects

Testability features and the testability access of the Alpha 21164 microprocessor

Test synthesis in the microprocessor product development cycle

Arithmetic built-in self-test for digital signal processing architectures

Reduced power consumption and EMI, high efficiency high frequency crystal oscillator

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Technology decomposition for low-power synthesis

Content Provider	IEEE Xplore Digital Library
Author	Panda, R. Najm, F.N.
Copyright Year	1995
Description	Author affiliation: Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA (Panda, R.; Najm, F.N.)
Abstract	Technology decomposition and technology mapping are two potential stages for minimizing circuit power during logic synthesis. Since power in CMOS circuits is directly dependent on the extent of circuit switching activity, we present a novel procedure to construct a low-activity circuit structure in the technology decomposition stage. This would result in low-power circuits when mapped. The algorithm uses the transition density as a measure of switching activity and is applicable to both synchronous and asynchronous static circuits. Our results show power reductions of up to 48% (on average /spl ap/10%), with little area or delay penalty.
Starting Page	627
Ending Page	630
File Size	427124
Page Count	4
File Format	PDF
ISBN	0780325842
DOI	10.1109/CICC.1995.518261
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits CMOS technology Clocks Circuit synthesis Switching circuits Delay Logic devices Steady-state Logic circuits Signal synthesis
Content Type	Text
Resource Type	Article

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