NDLI: Hierarchical timing-driven floorplanning and place and route using a timing budgeter

Content Provider	IEEE Xplore Digital Library
Author	Venkatesh, S.V.
Copyright Year	1995
Description	Author affiliation: Cadence Design Syst. Inc., San Jose, CA, USA (Venkatesh, S.V.)
Abstract	This paper describes a method to design large high-performance circuits using a tool called the Timing Budgeter to perform timing-driven hierarchical design. Present approaches to hierarchical timing-driven design are inadequate. Hierarchical design with considerations of timing typically requires the help of a timing expert to allocate and reallocate budgets of timing constraints to the blocks of a hierarchical design, as the design progresses. This approach is characterized by non-optimal timing budget allocations and tedious manual intervention. Another proposed method requires expensive iterations between physical layout and timing analysis. The hierarchical timing-driven methodology using the timing budgeter provides an automated method to allocate and reallocate high quality budgets to blocks of a hierarchical design. The methodology vastly improves the chance of satisfying the timing constraints of a large hierarchical design in one iteration of physical layout and timing analysis.
Starting Page	469
Ending Page	472
File Size	450130
Page Count	4
File Format	PDF
ISBN	0780325842
DOI	10.1109/CICC.1995.518226
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Design methodology Circuits Rivers Process design Design optimization Iterative methods Financial management Algorithm design and analysis Wire
Content Type	Text
Resource Type	Article

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