NDLI: Design of sequential machines for efficient test generation

Content Provider	IEEE Xplore Digital Library
Author	Cheng, K.-T. Agrawal, V.D.
Copyright Year	1989
Description	Author affiliation: AT&T Bell Lab., Murray Hill, NJ, USA (Cheng, K.-T.; Agrawal, V.D.)
Abstract	The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method.<>
Starting Page	358
Ending Page	361
File Size	403204
Page Count	4
File Format	PDF
ISBN	0818619864
DOI	10.1109/ICCAD.1989.76969
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential analysis Circuit testing Logic testing Pipelines Design for testability Logic design Circuit synthesis State feedback Sequential circuits Circuit faults
Content Type	Text
Resource Type	Article

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