NDLI: Fault detection and location in reconfigurable VLSI arrays

Content Provider	IEEE Xplore Digital Library
Author	Wang, K. Kuo, S.-Y.
Copyright Year	1989
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA (Wang, K.; Kuo, S.-Y.)
Abstract	A systematic and efficient fault diagnosis methodology in reconfigurable VLSI array architectures is presented. This methodology utilizes the output data path independence of subsets of processing elements (PEs) based on the topology of the arrays. The 'divide the conquer' technique is applied to reduce testing complexity and enhances the controllability and observability of arrays. An array under test is divided into several nonoverlapping parallel partitions. Those PEs in the same partition can be diagnosed simultaneously. The problem to find parallel partitions is shown equivalent to a generalized Eight Queens problem. Three types of easily testable PEs are designed to illustrate this approach. The main contribution of this paper is a novel PE fault diagnosis approach which speeds up the testing by at least O( mod V mod /sup 1/2/) for the arrays considered, where mod V mod is the number of PEs. This approach requires little or no hardware overhead depending on the types of architectures and can diagnose multiple PE faults.<>
Starting Page	234
Ending Page	237
File Size	287397
Page Count	4
File Format	PDF
ISBN	0818619864
DOI	10.1109/ICCAD.1989.76943
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Very large scale integration Testing Hardware Systolic arrays Fault diagnosis Voting Switches Multiplexing Electrical fault detection
Content Type	Text
Resource Type	Article

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