NDLI: Formulae and applications of interconnect estimation considering shield insertion and net ordering

Content Provider	IEEE Xplore Digital Library
Author	Ma, J.D.Z. Lei He
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA (Ma, J.D.Z.)
Abstract	It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an area-efficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the min-area SINO/R solution. In order to accommodate pre-routed P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient two-phase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Further, we develop various pre-layout estimation formulae for shielding areas and optimal P/G structures under different routing styles. These formulae can be readily used to guide global routing and high-level design decisions.
Starting Page	327
Ending Page	332
File Size	593433
Page Count	6
File Format	PDF
ISBN	0780372476
ISSN	10923152
DOI	10.1109/ICCAD.2001.968641
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Wires Coupling circuits Wiring Noise reduction Fabrics Delay Crosstalk Circuits and systems Switches
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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