NDLI: A system for synthesizing optimized FPGA hardware from Matlab(R)

Content Provider	IEEE Xplore Digital Library
Author	Haldar, M. Nayak, A. Choudhary, A. Banerjee, P.
Copyright Year	2001
Abstract	Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware.
Starting Page	314
Ending Page	319
File Size	1053154
Page Count	6
File Format	PDF
ISBN	0780372476
ISSN	10923152
DOI	10.1109/ICCAD.2001.968639
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Hardware Computer languages Computer architecture Throughput Time to market MATLAB Optimizing compilers Parallel processing Pipeline processing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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