NDLI: Miller factor for gate-level coupling delay calculation

Content Provider	IEEE Xplore Digital Library
Author	Pinhong Chen Kirkpatrick, D.A. Keutzer, K.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Pinhong Chen)
Abstract	In coupling delay computation, a Miller factor of more than 2/spl times/ may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5V/sub DD/ as the switching threshold voltage, an upper bound of 3/spl times/ for maximum delay and a lower bound of -1/spl times/ for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.
Starting Page	68
Ending Page	74
File Size	619371
Page Count	7
File Format	PDF
ISBN	0780364457
ISSN	10923152
DOI	10.1109/ICCAD.2000.896453
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coupling circuits Capacitance Delay estimation Threshold voltage Zero voltage switching Charge transfer Upper bound Crosstalk Timing SPICE
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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