NDLI: On diagnosis and correction of design errors

Please wait, while we are loading the content...

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

Leee/acm International Conference On Computer-aided Design Digest Of Technical Papers

New methods for parallel pattern fast fault simulation for synchronous sequential circuits

Fault behavior dictionary for simulation of device-level transients

New methods of improving parallel fault simulation in synchronous sequential circuits

Exploiting hardware sharing in high-level synthesis for partial scan optimization

High level synthesis for reconfigurable datapath structures

An improved method for RTL synthesis with testability tradeoffs

Interleaving based variable ordering methods for ordered binary decision diagrams

Dynamic variable ordering for ordered binary decision diagrams

Breadth-first manipulation of very large binary-decision diagrams

An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules

Simulating 3-D retarded interconnect models using complex frequency hopping (CFH)

Bounds on net lengths for high-speed PCBs

A net-oriented method for realistic fault analysis

On-chip test generation for combinational circuits by LFSR modification

Fault-based automatic test generator for linear analog circuits

A grid-based approach for connectivity binding with geometric costs

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's

Design tool integration using object-oriented database views

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

Cube-packing and two-level minimization

Combining technology mapping and placement for delay-optimization in FPGA designs

Parallel timing simulation on a distributed memory multiprocessor

Event driven adaptively controlled explicit simulation of integrated circuits

Simulating sigma-delta modulators in AWEswit

Practical applications of an efficient time separation of events algorithm

Min-max linear programming and the timing analysis of digital circuits

Minimum padding to satisfy short path constraints

A combined hierarchical placement algorithm

Efficient and effective placement for very large circuits

SEFOP: A novel approach to data path module placement

Computing the observable equivalence relation of a finite state machine

Algebraic decision diagrams and their applications

Representation and symbolic manipulation of linearly inductive Boolean functions

Test quality and yield analysis using the DEFAM defect to fault mapper

Convexity-based algorithms for design centering

STYLE: A technology-independent approach to statistical design

Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Efficient estimation of dynamic power consumption under a real delay model

Architecture and routability analysis for row-based FPGAs

Partitioning with cone structures

A timing driven N-way chip and multi-chip partitioner

Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs

Unifying synchronous/asynchronous state machine synthesis

Efficient verification of determinate speed-independent circuits

Accelerated waveform methods for parallel transient simulation of semiconductor devices

An accurate grid local truncation error for device simulation

A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structures

The practical application of retiming to the design of high-performance systems

Performance-driven partitioning using retiming and replication

Retiming gated-clocks and precharged circuit structures

Sequential logic optimization by redundancy addition and removal

The maximum set of permissible behaviors for FSM networks

Input don't care sequences in FSM networks

A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits

Macromodeling of the AC characteristics of CMOS op-amps

Nyquist data converter testing and yield analysis using behavioral simulation

Run-time requirement tracing

A flow-based user interface for efficient execution of the design cycle

A visual design environment

New faster Kernighan-Lin-type graph-partitioning algorithms

An algorithm for improving partitions of pin-limited multi-chip systems

Transforming an arbitrary floorplan into a sliceable one

State look ahead technique for cycle optimization of interacting finite state Moore machines

Retiming sequential circuits for low power

A symbolic algorithm for maximum flow in 0-1 networks

Generalized constraint generation for analog circuit design

Latchup-aware placement and parasitic-bounded routing of custom analog cells

A unified approach to simulating electrical and thermal substrate coupling interactions in ICs

Test generation for path delay faults based on learning

Test generation for multiple faults based on parallel vector pair analysis

Boolean algebraic test generation using a distributed system

Scheduling for minimum dependence in FSMs

High throughput pipelined data path synthesis by conserving the regularity of nested loops

Execution interval analysis under resource constraints

Inverter minimization in multi-level logic networks

A simple algorithm for fanout optimization using high-performance buffer libraries

Boolean matching for full-custom ECL gates

Switch module design with application to two-dimensional segmentation design

Routing for symmetric FPGAs and FPICs

A new generalized row-based global router

On diagnosis and correction of design errors

Fault dictionary compression and equivalence class computation for sequential circuits

Tri-state bus conflict checking method for ATPG using BDD

Instruction set mapping for performance optimization

Quadratic zero-one programming based synthesis of application specific data paths

An ASIP instruction set optimization algorithm with functional module sharing constraint

Verification of large synthesized designs

HANNIBAL: An efficient tool for logic verification based on recursive learning

Probabilistic construction and manipulation of Free Boolean Diagrams

Wire Length And Delay Minimization In General Clock Net Routing

Skew And Delay Optimization For Reliable Buffered Clock Trees

Delay Minimization For Zero-skew Routing

How To Do Weighted Random Testing For Bist?

An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers

Cellular Automata Synthesis Based On Precomputed Test Vectors For Built-in Self-test

Tree-based mapping of algorithms to predefined structures

Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors

Rapid prototyping of microprocessor-based systems

Boolean factorization using multiple-valued minimization

Modeling hierarchical combinational circuits

Analysis of cyclic combinational circuits

Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models

Optimal wiresizing under the distributed Elmore delay model

An efficient algorithm for the net matching problem

Logic partitioning to pseudo-exhaustive test for BIST design

Cellular automata based synthesis of easily and fully testable FSMs

Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards

Sizing and verification of communication buffers for communicating processes

Buffer assignment for data driven architectures

Exact evaluation of memory size for multi-dimensional signal processing systems

Maximum projections of don't care conditions in a Boolean network

Detection of symmetry of Boolean functions represented by ROBDDs

FGILP: An integer linear program solver based on function graphs

Minimum crosstalk channel routing

A spacing algorithm for performance enhancement and cross-talk reduction

A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths

Reconfigurable scan chains: A novel approach to reduce test application time

Augmented partial reset

Merging multiple FSM controllers for DFT/BIST hardware

Allocation of multiport memories for hierarchical data streams

Behavior tables: A basis for system representation and transformational system synthesis

A general consistency technique for increasing the controllability of high level synthesis tools

Efficient modeling of switch-level networks containing undetermined logic node states

Piecewise linear models for Rsim

Parallel multi-delay simulation

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures

A fast algorithm for VLSI net extraction

A new feed-through assignment algorithm based on a flow model

1992 IEEE/ACM International Conference on Computer-Aided Design

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

On diagnosis and correction of design errors

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I. Reddy, S.M.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Pomeranz, I.)
Abstract	We consider the problem of diagnosing and correcting two classes of design errors, called output correspondence and input correspondence errors. Under these errors, the order of the outputs or inputs of the implementation are changed, such that an incorrect matching between specification and implementation outputs or inputs is obtained. These errors were not included in earlier methods proposed to diagnose and correct design errors. We present diagnosis and correction procedures for these errors, and discuss the performance of these procedures in the presence of previously studied design errors. The analysis shows the importance of considering output and input correspondence errors as part of a complete correction procedure.
Starting Page	500
Ending Page	507
File Size	969225
Page Count	8
File Format	PDF
ISBN	0818644907
DOI	10.1109/ICCAD.1993.580104
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction Circuits Computer errors Design engineering Cities and towns Error analysis Hardware Boolean functions Routing
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in