NDLI: Cube-packing and two-level minimization

Content Provider	IEEE Xplore Digital Library
Author	Murgai, R. Brayton, R.K. Sangiovanni-Vincentelli, A.
Copyright Year	1993
Description	Author affiliation: Dept. of EECS, California Univ., Berkeley, CA, USA (Murgai, R.)
Abstract	Almost all mapping tools for programmable gate arrays (PGAs) start from a network optimized for the number of literals in the factored form. However, PGA architectures imposed different kinds of constraints on the synthesis process. For example, table look up (TLU) architectures restrict each function to at most m inputs (for a fixed m). This is unlike any type of constraint in PLA or standard-cell synthesis. Thus, standard cost functions like the number of cubes or factored form literals are not necessarily good complexity measures for TLU architectures. Decomposition and block count minimization are two steps in PGA mapping that are applied to an optimized design. In decomposition, a feasible representation of the network is obtained, which can be mapped directly onto the target architecture. Block count minimization then tries to maximally group the functions of the decomposed network into basic blocks such that the total number of blocks used are minimized. We address the problem of modeling the decompositon step, in optimization; in particular, we look at cube-packing, which has proved quite effective for the TLU architectures. We propose a technique for deriving a two-level representation of a logic function which yields better results after cube-packing. The technique rests on the idea of using the support of a set of primes as the basic object is two-level minimization, as opposed to a prime. Experiments indicate an average improvement of 12.5% over standard two-level methods.
Starting Page	115
Ending Page	122
File Size	781271
Page Count	8
File Format	PDF
ISBN	0818644907
DOI	10.1109/ICCAD.1993.580041
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Minimization Cost function Network synthesis Programmable logic arrays Design optimization Logic functions Measurement standards Boolean functions Surges
Content Type	Text
Resource Type	Article

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