NDLI: Architecture and routability analysis for row-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Pedram, M. Nobandegani, B.S. Preas, B.T.
Copyright Year	1993
Description	Author affiliation: Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA (Pedram, M.)
Abstract	FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. One class of FPGAs has rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. This class has the flavor of traditional channeled gate arrays or standard cells and is exemplified by the Actel family of FPGAs. However, unlike conventional standard cell designs, the FPGA routing channels contain predefined wiring segments of various lengths which may be interconnected using antifuses. This paper develops analytical models that permit the design of FPGA routing channels and the analysis of the routability of row-based FPGAs devices based on a generic characterization of the row-based FPGA routing algorithms. In particular, it demonstrates that (using probabilistic models for the origination point and length for connections) an FPGA with properly designed segment length and distribution can be nearly as efficient as a mask-programmable channel (in terms of number of tracks required for routing a given interconnection specification). Experimental results corroborate this prediction. In addition, this paper provides a method for evaluating various channel architectures.
Starting Page	230
Ending Page	235
File Size	683897
Page Count	6
File Format	PDF
ISBN	0818644907
DOI	10.1109/ICCAD.1993.580062
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Logic devices Routing Logic design Logic arrays Algorithm design and analysis Very large scale integration Production Time to market Wiring
Content Type	Text
Resource Type	Article

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