NDLI: Modelling and testing the impact of hot solder dip process on leaded components

Content Provider	IEEE Xplore Digital Library
Author	Stoyanov, S. Best, C. Alam, M.O. Bailey, C. Tollafield, P. Parker, M. Scott, J.
Copyright Year	2012
Description	Author affiliation: Centre of Numerical Modelling and Process Analysis, University of Greenwich, London UK (Stoyanov, S.; Best, C.; Alam, M.O.; Bailey, C.) \|\| Micross Components Ltd, Lancasterfields, UK (Tollafield, P.; Parker, M.) \|\| SELEX Galileo Ltd, Edinburgh, UK (Scott, J.)
Abstract	The use of microelectronics components with lead-free solder finishes on their terminations in high reliability and safety critical defence and aerospace equipment is associated with major long-term reliability issues due to tin-whisker growth phenomena. A potential solution to this problem is to “re-finish” the package terminations by removing the tin coating from the leads and replace with conventional tin-lead solder in a post-manufacturing process known as hot solder dip (HSD). This paper details a modelling approach to the thermo-mechanical characterisation of leaded components subjected to a double-dip HSD process. Transient thermal finite element analysis (FEA) is used to evaluate the temperature distribution and gradients in a QFP-type component and then used as thermal loads to predict the stress evolution in the package. The risk of thermally induced damage in the part at package level is assessed using the model predictions and compared with findings from electrical and CSAM tests undertaken on a pre- and post- refinished samples. It is concluded that in the instance of the studied part no thermo-mechanical damage is induced as a result of the HSD.
Starting Page	303
Ending Page	308
File Size	1593081
Page Count	6
File Format	PDF
ISBN	9781467322416
ISSN	21612536
e-ISBN	9781467322409
e-ISBN	9781467322393
DOI	10.1109/ISSE.2012.6273091
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-09
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Electronic packaging thermal management Predictive models Copper Thermal stresses Wires Thermomechanical processes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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