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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shenjie Wang Dehollain, C. |
| Copyright Year | 2013 |
| Description | Author affiliation: RFIC Group, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland (Shenjie Wang; Dehollain, C.) |
| Abstract | A 460 kS/s 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with rail-to-rail input range is proposed for acquiring capacitive sensor. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor (SC) capacitance-to-voltage converter (C2V). A bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is realized by a single-ended cascaded binary-weighted (CBW) capacitive digital-to-analog converter (DAC). Self-timing SAR logic borrows extra half cycle relaxing the settling of preamps and reduces the power consumption. At a sample rate of 460 kS/s, the 10-bit SAR ADC achieves an ENOB of 9.9 bit and consumes 35 μW with 1.8 V power supply, resulting in an energy efficiency of 80 fJ/step. The circuits are designed and simulated with parasitic models using a commercially available 180 nm CMOS process. |
| Sponsorship | IEEE |
| Starting Page | 453 |
| Ending Page | 456 |
| File Size | 683510 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479924523 |
| DOI | 10.1109/ICECS.2013.6815452 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-08 |
| Publisher Place | United Arab Emirates |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Noise Capacitors Linearity Approximation methods Capacitance Accuracy |
| Content Type | Text |
| Resource Type | Article |
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